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Quartus II

This page contains information about Quartus II, the fully IDE from Altera. You can find here tutorials, sample projects and information. It is intended for everyone who wants to learn more on digital design using Quartus II.

Most sample projects are based on the VHDL description language, but projects created with schematic diagrams will be added over time.

Beware that some of the documents are written in Dutch.


Tutorial Schematic Entry (updated, Dutch, 17-09-2018)
This tutorial covers the entry of a digital system using schematic entry such as logic gates. The use of sub design, creating hierarchy, is also covered. The creation of a project, connecting inputs and outputs to the device pins and simulation are not covered. When using this tutorial, additional settings are needed. These files can be found here.

Tutorial VHDL Entry (Dutch, 05-02-2018)
This tutorial covers the entry of a digital system using VHDL. The creation of a project, connecting inputs and outputs to the device pins and simulation are also covered. The tutorial includes a list of pin connections to switches, leds en seven segment displays.

Using Block Design Files with ModelSim (updated, English, 20-09-2018)
Schematic designs are saved in Block Design Files. Simulation using ModelSim is not directly possible, the design files have to be converted to VHDL or Verilog files. This set of files, including documentation, takes care of this problem.

Default Pin Assignments for DE0 Board
All pin assignments of the DE0 board can be found in the file default_pin_assignments_DE0.qsf. It's really a Tcl script that can be imported into Quartus. First, download the script and place it in the project directory. Then open the menu Assignments→Import Assignments. In the dialog that follows, select the file and press OK. The assigments will be read into the current project. Of course your project has to be open.

Tutorial State Machine Entry (Dutch, 29-04-2014)
This tutorial handles the entry of state machines with state diagrams in Quartus. In the first chapter, the editor is presented. The second chapter describes how a state machine is entered. The third chapter deals with the so-called Registered output & current/next clock cycle options. The state diagrams can be converted to VHDL or Verilog descriptions. Written by one of my students.

Installation of Quartus 13.0sp1/ModelSim 10.1d (Dutch, 6-8-2016)
These manuals will guide you through the installation process of Quartus 13.0sp1 and ModelSim 10.1d on Windows and Linux and include sections on how to install the USB-Blaster drivers on the subsequent OSes. Note that Quartus doesn't run on OS-X. Version 13.0sp1 is the last version that support both the Cyclone II (e.g. DE2-70 board) and Cyclone III (e.g. DE-0 board).

Ring counters (English)
This paper presents some insight in the construction and use of ring counters. LaTeX source provided.

Quartus/ModelSim Projects (Dutch/English documentation)

inldig_gates - A schematic logic design using the standard gates AND, OR, NOT and EXOR. Includes an XOR constructed from four NANDs. Synthesis for DE-0 board and simulation supported.
inldig_bcd_adder - A schematic logic design of an one-digit BCD adder.
inldig_dflipflops - A schematic logic design of a T-flipflop and a D-flopflop.

digse1_half_adder - A dataflow description of an half adder with XOR- and AND ports.
digse1_nand2 - A dataflow description of a NAND port described with std_ulogic.
digse1_nor3 - A dataflow description of a 3-input NOR port described with std_logic.
digse1_prior - An example of a Concurrent Signal Assignment, results in a priority encoder.
digse1_agtb - An example of a "greater than" circuit (unsigned).
digse1_mux4 - An example of a Selected Signal Assignment - results in a 4-input multiplexer.
digse1_full_adder_ssa - A full adder described using a SSA/truth table.
digse1_vhdl_tristate_example - shows the difference between std_ulogic en std_logic. Simulation and synthesis possible.
digse1_delta_delay - Shows how delta delays are used in two cascaded inverters. Simulation only.
digse1_seq_statements - Some examples of sequential statements, including D latch and D flip-flop.
digse1_exor_sim - Shows how the simulator handles the absence of delays ('after' and delta delays). Simulation only.
digse1_big_multinor - Shows how generic constants can be used at instantiation time.
digse1_big_multinor_alt - Alternative version.
digse1_struct_xor4nands - Shows how to describe a XOR port using four NANDS and hierachies.
digse1_tflipflop- Description of a T-flipflop, the accent is on simulation.
digse1_counter_4bit - A description of a 4-bit up counter with testbench.
digse1_counter_bcd - A BCD decade up counter with testbench.
digse1_fa_4bit - A 4-bit full adder using '+' with testbench.
digse1_sin_gen - A 16-step, 4-bit wide digital sine wave generator with testbench (for use with DE0 board).
digse1_counter_integer - A up counter with the use of integers.
digse1_pwm_8bit - An 8 bit digital PWM system.
digse1_johnson_counter - Generic description of a Johnson counter.
digse1_reset_synchronizer - A description of a reset synchronizer circuit.

digse2_mealy_example - An example of a Mealy machine with two states.
digse2_moore_example - An example of a Moore machine with three states.
digse2_herk110 - Recognizer for the pattern 110.
digse2_seq_mult_2 - Example of a sequential multiplier with testbench using sepatated control and datapath.
digse2_seq_mult_2_fsmd - Example of a sequential multiplier with integrated datapath (FSMD)
digse2_seq_mult_2_algo - Example of a sequential multiplier written in a more algorithic way.
digse2_stopwatch - A very simple stopwatch..
digse2_microprocessor - Complete VHDL description of a simple 4-register, 8-bit microprocessor with a number of programming examples. The processor has no stack and no interrupts. It can handle only unsigned numbers. It is not intended as a full-fledged uP, merely to show how a basic uP works and can be written in VHDL.
digse2_sasm - Very simple command line assembler for the microprocessor. It assembles a file into VHDL ROM statements to be used in the VHDL code of the microprocessor.

prodig_lcd_driver_hd44780 - Complete VHDL description of a driver for the well-known HD44780 LCD-driver IC used in many 16x2 LCD's. Can be used up to 16x4 characters. There is an example on how to use it in your HDL project. Simulation possible. Direct synthesis for DE0 board. This project is published on OpenCores.

prodig_ad7813_sim - Complete VHDL description of the AD7813 Analog-to-Digital Converter. After synthesis, this description simulates an AD7813 on a DE0 board. The "analog" input is realised using onboard switches. The description can also be used for simulation as part of a bigger system.

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